AMBA is a solution for the blocks to interface with each other. The objective of the AMBA specification is to: facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors, be technology independent, to allow reuse of IP cores , peripheral and system macrocells across diverse IC processes, encourage modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries minimize silicon infrastructure while supporting high performance and low power on-chip communication. AMBA protocol specifications[ edit ] The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. It is supported by ARM Limited with wide cross-industry participation. A simple transaction on the AHB consists of an address phase and a subsequent data phase without wait states: only two bus-cycles.

Author:Kazragar Kigakinos
Language:English (Spanish)
Published (Last):2 June 2005
PDF File Size:2.76 Mb
ePub File Size:2.96 Mb
Price:Free* [*Free Regsitration Required]

Given the large number of designs that use these you definitely would want to be aware of these and learn some of them in depth to upgrade your skills.

The primary motivation of AMBA protocols is to have a standard and efficient way to interconnecting these blocks with re-use across multiple designs. The first step in learning AMBA protocols is to understand where exactly these different protocols are used , how these evolved and how all of them fit into a SOC design. Following diagram reference from the AMBA 2. Further in , an enhanced version was introduced — AXI 4. Following diagram illustrates this evolution of protocols along with the SOC design trends in industry.

Following diagram illustrates how an AXI interconnect can be used to build an SOC with various functional blocks talking through a master-slave protocol. Lastly, in the current era of heterogeneous computing for HPC and data center markets, the integration trend continues with increasing number of processor cores along with several heterogeneous computing elements like GPU, DSP, FPGAs, memory controllers and IO sub systems.

Now that hopefully you understand how the protocols evolved and how each of them fit in to an SOC design— here are few basics and references to resources that you can use to learn more in depth about each of the protocol. ARM has open sourced all of the protocols and all the specifications can be downloaded from the ARM website free by signing up.

The reads and writes shares the same set of signals and no burst data transfers are supported. The latest spec APB 2.

These could be a internal memory or an external memory interface, DMA , DSP etc but the shared bus would limit the number of agents. Similar to APB, this is a shared bus protocol for multiple masters and slaves, but higher bandwidth is possible through burst data transfers.

The simplification comes with support for only a single master design and that removes need for any arbitration, retry, split transactions etc. This is a point to point interconnect and overcomes the limitations of a shared bus protocol in terms of number of agents that can be connected.

The protocol also was an enhancement from AHB in terms of supporting multiple outstanding data transfers pipe-lined , burst data transfers, separate read and write paths and supporting different bus widths. AXI-lite protocol is a simplified version of AXI and the simplification comes in terms of no support for burst data transfers. AXI-stream protocol is another flavor of the AXI protocol that supports only streaming of data from a master to a slave.

Multiple streams of data can be transferred even with interleaving across a master and slave. This becomes useful in designs like video streaming applications. The AXI-stream protocol has a different spec and is available here for download. The ACE protocol extends the AXI read and write data channels by introducing separate snoop address, snoop data and snoop response channels. These extra channels provides mechanisms to implement a snoop based coherency protocol.

If you are new to coherency, understanding that will be a pre-requisite before learning ACE protocol. The CHI protocol uses a layered packet based communication protocol with protocol, link layer and physical layer implementation and also supports QoS based flow control and retry mechanisms.

Hope this gives an overview and helps getting started to learn more in depth into these protocols. The best way to learn further is to read the specifications to understand details of each protocol.





Advanced Microcontroller Bus Architecture


Related Articles